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» System Level Simulation of LTE Networks
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NOCS
2007
IEEE
15 years 3 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
AINA
2007
IEEE
15 years 3 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
HPCA
2000
IEEE
15 years 1 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
GECCO
2004
Springer
15 years 2 months ago
Evolved Motor Primitives and Sequences in a Hierarchical Recurrent Neural Network
This study describes how complex goal-directed behavior can evolve in a hierarchically organized recurrent neural network controlling a simulated Khepera robot. Different types of ...
Rainer W. Paine, Jun Tani
DATE
2010
IEEE
121views Hardware» more  DATE 2010»
15 years 2 months ago
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...
Sven van Haastregt, Eyal Halm, Bart Kienhuis