897 search results - page 119 / 180 » System-Level Design for FPGAs |
172
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ISVLSI
2008
IEEE
15 years 11 months ago
2008
IEEE
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
127
Voted
AHS
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
146
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ASAP
2006
IEEE
15 years 10 months ago
2006
IEEE
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
114
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— We propose a new crossbar switch structure with adaptive bandwidth control. In a complex SoC design, the proposed crossbar switch efficiently incorporates various IPs with diff...
141
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ARCS
2005
Springer
15 years 10 months ago
2005
Springer
Dynamic Reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting...