897 search results - page 77 / 180 » System-Level Design for FPGAs |
130
click to vote
DDECS
2007
IEEE
15 years 10 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
147
click to vote
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for thes...
140
click to vote
FCCM
2002
IEEE
15 years 9 months ago
2002
IEEE
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
138
click to vote
ERSA
2004
15 years 5 months ago
2004
This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Throu...
140
click to vote
ERSA
2010
15 years 2 months ago
2010
A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly imp...