217 search results - page 10 / 44 » System-Level Modeling and Verification: a Comprehensive Desi... |
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
CODES
2008
IEEE
14 years 9 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
DAC
1996
ACM
15 years 1 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...