217 search results - page 19 / 44 » System-Level Modeling and Verification: a Comprehensive Desi... |
130
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
131
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UML
2004
Springer
15 years 9 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
132
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ASE
2008
15 years 4 months ago
2008
Model checkers were originally developed to support the formal verification of high-level design models of distributed system designs. Over the years, they have become unmatched in...
130
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DAC
1996
ACM
15 years 8 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
124
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ASPDAC
2007
ACM
15 years 8 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...