30 search results - page 5 / 6 » Tableaux and Model Checking for Memory Logics |
122
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VLSID
2001
IEEE
16 years 2 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
132
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IEEEPACT
2006
IEEE
15 years 7 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
KBSE
2007
IEEE
15 years 8 months ago
2007
IEEE
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
137
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DAC
1996
ACM
15 years 6 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
151
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SIGSOFT
2006
ACM
15 years 7 months ago
2006
ACM
Bitwise operations are commonly used in low-level systems code to access multiple data fields that have been packed into a single word. Program analysis tools that reason about s...