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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 5 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
94
Voted
IPSN
2005
Springer
15 years 5 months ago
eBlocks - an enabling technology for basic sensor based systems
—We describe the development of a set of embedded system building blocks, known as eBlocks. An eBlock network can be viewed as a basic form of sensor network that can be develope...
Susan Cotterell, Ryan Mannion, Frank Vahid, Harry ...
110
Voted
DATE
1999
IEEE
172views Hardware» more  DATE 1999»
15 years 4 months ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
15 years 3 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
NIPS
1998
15 years 29 days ago
Semi-Supervised Support Vector Machines
We introduce a semi-supervised support vector machine (S3 VM) method. Given a training set of labeled data and a working set of unlabeled data, S3 VM constructs a support vector m...
Kristin P. Bennett, Ayhan Demiriz