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» Task Graph Scheduling Using Timed Automata
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RSP
2007
IEEE
143views Control Systems» more  RSP 2007»
15 years 7 months ago
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
Ewerson Carvalho, Ney Calazans, Fernando Moraes
CAV
2010
Springer
239views Hardware» more  CAV 2010»
15 years 3 months ago
Universal Causality Graphs: A Precise Happens-Before Model for Detecting Bugs in Concurrent Programs
Triggering errors in concurrent programs is a notoriously difficult task. A key reason for this is the behavioral complexity resulting from the large number of interleavings of op...
Vineet Kahlon, Chao Wang
LCTRTS
2000
Springer
15 years 5 months ago
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Matteo Corti, Roberto Brega, Thomas R. Gross
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
15 years 5 months ago
Optimal code generation for embedded memory non-homogeneous register architectures
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
Guido Araujo, Sharad Malik
ISLPED
1996
ACM
91views Hardware» more  ISLPED 1996»
15 years 5 months ago
Energy minimization using multiple supply voltages
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling pro...
Jui-Ming Chang, Massoud Pedram