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107
Voted
ATS
2009
IEEE
15 years 10 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
124
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DDECS
2006
IEEE
15 years 9 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
126
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ISCAS
1999
IEEE
15 years 7 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
115
Voted
CGVR
2006
15 years 4 months ago
2006
- This paper presents a technique of evolutionary design for plants in virtual worlds, inspired from Richard Dawkins' adaptive walks within the space of biomorph structures. T...
131
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SLIP
2009
ACM
15 years 9 months ago
2009
ACM
Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interco...