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» Techniques for increasing effective data bandwidth
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ISCAS
2007
IEEE
148views Hardware» more  ISCAS 2007»
15 years 3 months ago
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter
— Mismatches between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) cause undesirable distortions in the output spectrum. To reduce t...
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
15 years 3 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
WMPI
2004
ACM
15 years 2 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
CSDA
2006
142views more  CSDA 2006»
14 years 9 months ago
A Bayesian approach to bandwidth selection for multivariate kernel density estimation
: Kernel density estimation for multivariate data is an important technique that has a wide range of applications. However, it has received significantly less attention than its un...
Xibin Zhang, Maxwell L. King, Rob J. Hyndman
ISCA
1996
IEEE
126views Hardware» more  ISCA 1996»
15 years 1 months ago
Memory Bandwidth Limitations of Future Microprocessors
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
Doug Burger, James R. Goodman, Alain Kägi