83 search results - page 2 / 17 » Technology Mapping for Reliability Enhancement in Logic Synt... |
TCAD
2008
13 years 5 months ago
2008
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
GLVLSI
2007
IEEE
14 years 17 days ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
GLVLSI
2006
IEEE
14 years 9 days ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
FPGA
2007
ACM
14 years 12 days ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...