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ISQED
2006
IEEE
176views Hardware» more  ISQED 2006»
14 years 7 days ago
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
Zhiyu Liu, Volkan Kursun
GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
14 years 8 days ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
FPL
2000
Springer
130views Hardware» more  FPL 2000»
13 years 9 months ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
13 years 10 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
ICCAD
2004
IEEE
123views Hardware» more  ICCAD 2004»
14 years 3 months ago
Logical effort based technology mapping
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
Shrirang K. Karandikar, Sachin S. Sapatnekar