27 search results - page 3 / 6 » Temperature-aware routing in 3D ICs |
74
Voted
ICCAD
2007
IEEE
15 years 7 months ago
2007
IEEE
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
75
Voted
NOCS
2010
IEEE
14 years 8 months ago
2010
IEEE
—Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D IC technology, is motivated to achieve lower latency, lower power consumption, and higher ...
81
Voted
ICCAD
2005
IEEE
15 years 7 months ago
2005
IEEE
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
181
Voted
DAC
2011
ACM
13 years 10 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
84
Voted
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...