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» Temporal Logic Model Checking (Abstract)
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DAC
1998
ACM
16 years 2 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
ATAL
2009
Springer
15 years 8 months ago
Rational play and rational beliefs under uncertainty
Alternating-time temporal logic (atl) is one of the most influential logics for reasoning about agents’ abilities. Constructive Strategic Logic (csl) is a variant of atl for im...
Nils Bulling, Wojciech Jamroga
MJ
2006
102views more  MJ 2006»
15 years 1 months ago
Hybrid verification integrating HOL theorem proving with MDG model checking
In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and (multiway decision graphs) model checker. Our ...
Rabeb Mizouni, Sofiène Tahar, Paul Curzon
MONTEREY
2007
Springer
15 years 7 months ago
Logic-Based Regulatory Conformance Checking
In this paper, we describe an approach to formally assess whether an organization conforms to a body of regulation. Conformance is cast as a model checking question where the regul...
Nikhil Dinesh, Aravind K. Joshi, Insup Lee, Oleg S...
WWW
2006
ACM
16 years 2 months ago
A framework for XML data streams history checking and monitoring
The need of formal verification is a problem that involves all the fields in which sensible data are managed. In this context the verification of data streams became a fundamental...
Alessandro Campi, Paola Spoletini