203 search results - page 6 / 41 » Test Generation and Fault Localization for Quantum Circuits |
ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
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DAC
2004
ACM
15 years 3 months ago
2004
ACM
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
CEC
2005
IEEE
15 years 5 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
ITC
1993
IEEE
15 years 3 months ago
1993
IEEE
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...