1016 search results - page 8 / 204 » Test Generation for Designs with On-Chip Clock Generators |
89
Voted
CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
ET
2002
14 years 11 months ago
2002
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
81
Voted
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
97
Voted
ET
2002
14 years 11 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
88
Voted
FCCM
2003
IEEE
15 years 5 months ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...