77 search results - page 13 / 16 » Test Generation for Global Delay Faults |
78
Voted
ATS
2000
IEEE
15 years 1 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
GLVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
ICSE
2003
IEEE-ACM
15 years 9 months ago
2003
IEEE-ACM
Web applications have become critical components of the global information infrastructure, and it is important that they be validated to ensure their reliability. Therefore, many ...
103
Voted
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper presents 3LSSD, a novel, easilyautomatable approach for scan insertion and ATPG of asynchronous circuits. 3LSSD inserts scan latches only into global circuit feedback p...