203 search results - page 29 / 41 » Test Pattern Generator for Delay Faults |
112
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VTS
1999
IEEE
15 years 6 months ago
1999
IEEE
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
140
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DAC
2003
ACM
15 years 7 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
ATS
2009
IEEE
15 years 8 months ago
2009
IEEE
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets,...
ATS
2009
IEEE
15 years 8 months ago
2009
IEEE
—Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the re...
120
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ET
2002
15 years 1 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...