203 search results - page 31 / 41 » Test Pattern Generator for Delay Faults |
117
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VLSID
2005
IEEE
16 years 2 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
DAC
2002
ACM
16 years 2 months ago
2002
ACM
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnos...
DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
TCAD
2010
14 years 8 months ago
2010
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
105
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...