203 search results - page 39 / 41 » Test Pattern Generator for Delay Faults |
VLSID
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
IOLTS
2008
IEEE
15 years 3 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
62
Voted
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
111
Voted
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...