22 search results - page 4 / 5 » Test Volume and Application Time Reduction Through Scan Chai... |
ATS
2004
IEEE
13 years 10 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
TVLSI
2008
13 years 6 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
DFT
2006
IEEE
14 years 9 days ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
TCAD
1998
13 years 5 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...