142 search results - page 4 / 29 » Test architecture design and optimization for three-dimensio... |
AAAI
2012
12 years 12 months ago
2012
This paper presents the design and learning architecture for an omnidirectional walk used by a humanoid robot soccer agent acting in the RoboCup 3D simulation environment. The wal...
115
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
73
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DAC
2007
ACM
15 years 10 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...