142 search results - page 5 / 29 » Test architecture design and optimization for three-dimensio... |
VTS
2003
IEEE
15 years 2 months ago
2003
IEEE
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
89
Voted
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
ET
2002
14 years 9 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
81
Voted
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
78
Voted
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...