5855 search results - page 57 / 1171 » Test generation and minimization with |
102
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ITC
1999
IEEE
15 years 5 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
114
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GLVLSI
2008
IEEE
15 years 7 months ago
2008
IEEE
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
DATE
2003
IEEE
15 years 6 months ago
2003
IEEE
Abstract : A novel design methodology for test pattern generation in BIST is presented. Here faults and errors in the generator itself are detected. Two different design methodolog...
ICSE
2010
IEEE-ACM
15 years 6 months ago
2010
IEEE-ACM
We present an approach for describing tests using nondeterministic test generation programs. To write such programs, we introduce UDITA, a Java-based language with non-determinist...
VTS
2002
IEEE
15 years 6 months ago
2002
IEEE
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...