624 search results - page 18 / 125 » Test set compaction algorithms for combinational circuits |
137
Voted
VLSID
1993
IEEE
15 years 8 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
154
click to vote
JISE
2000
15 years 3 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
126
click to vote
DAC
2005
ACM
15 years 5 months ago
2005
ACM
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
118
click to vote
ET
2002
15 years 3 months ago
2002
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
117
click to vote
ICCAD
2002
IEEE
16 years 25 days ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspeciļ¬c spectral information in th...