624 search results - page 18 / 125 » Test set compaction algorithms for combinational circuits |
VLSID
1993
IEEE
15 years 3 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
109
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JISE
2000
14 years 11 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
ET
2002
14 years 11 months ago
2002
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This...
86
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ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspeciļ¬c spectral information in th...