624 search results - page 19 / 125 » Test set compaction algorithms for combinational circuits |
FTCS
1993
15 years 1 months ago
1993
We present a new test response compression method called cumulative balance testing (CBT)that extends both balance testing and accumulatorcompression testing. CBT uses an accumulat...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
The development of new Field-Programmed, MaskProgrammed and Laser-Programmed Gate Array architectures is hampered by the lack of realistic test circuits that exercise both the arc...
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ATS
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
A special logic synthesis problem is considered for Boolean functions which have large don’t care sets and are irregular. Here, a function is considered as irregular if the inpu...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...