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» Test set compaction algorithms for combinational circuits
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ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
15 years 8 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann
134
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RAM
2008
IEEE
95views Robotics» more  RAM 2008»
15 years 10 months ago
A New Distance Algorithm and Its Application to General Force-Closure Test
This paper presents an algorithm for computing the distance between a point and a convex cone in n-dimensional space. The convex cone is specified by the set of all nonnegative com...
Yu Zheng, Chee-Meng Chew
173
Voted
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 10 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
142
Voted
EUROGRAPHICS
2010
Eurographics
16 years 1 months ago
HCCMeshes: Hierarchical-Culling oriented Compact Meshes
Hierarchical culling is a key acceleration technique used to efficiently handle massive models for ray tracing, collision detection, etc. To support such hierarchical culling, bo...
Tae-Joon Kim, Yongyoung Byun, Yongjin Kim, Bochang...
161
Voted
FGR
2008
IEEE
299views Biometrics» more  FGR 2008»
15 years 10 months ago
Face recognition with occlusions in the training and testing sets
Partial occlusions in face images pose a great problem for most face recognition algorithms. Several solutions to this problem have been proposed over the years – ranging from d...
Hongjun Jia, Aleix M. Martínez