624 search results - page 42 / 125 » Test set compaction algorithms for combinational circuits |
137
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DATE
2000
IEEE
15 years 8 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
143
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ICCAD
2009
IEEE
15 years 1 months ago
2009
IEEE
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
166
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KES
2008
Springer
15 years 4 months ago
2008
Springer
Evolutionary techniques provide powerful tools to design novel solutions for hard problems in different areas. However, the problem of scale (i.e. how to create a large, complex s...
162
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FMCAD
2000
Springer
15 years 7 months ago
2000
Springer
Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential...
125
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VLSID
1996
IEEE
15 years 8 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...