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70
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ICCAD
1996
IEEE
144views Hardware» more  ICCAD 1996»
15 years 4 months ago
Validation coverage analysis for complex digital designs
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
Richard C. Ho, Mark Horowitz
87
Voted
DC
2001
15 years 1 months ago
Qualified Dublin Core using RDF for Sci-Tech Journal Articles
As a participant in the D-Lib Test Suite project, the University of Illinois maintains a full-text XML testbed containing over 65,000 scientific and technical journal articles. Fo...
Thomas G. Habing, Timothy W. Cole, William H. Misc...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 6 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
94
Voted
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
15 years 4 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
ENASE
2011
219views Hardware» more  ENASE 2011»
14 years 8 days ago
Mutation Selection: Some Could be Better than All
In previous research, many mutation selection techniques have been proposed to reduce the cost of mutation analysis. After a mutant subset is selected, researchers could obtain a t...
Zhiyi Zhang, Dongjiang You, Zhenyu Chen, Yuming Zh...