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» Testing Digital Circuits with Constraints
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MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
15 years 4 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
IUI
1999
ACM
15 years 1 months ago
Integrating Organizational Memory and Performance Support
We describe an approach to building integrated performance support systems by using model-based task tracking to link performance support tools to video-based organizational memor...
Christopher R. Johnson, Lawrence Birnbaum, Ray Bar...
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
15 years 3 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
15 years 3 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
SIGSOFT
2003
ACM
15 years 10 months ago
ARCHER: using symbolic, path-sensitive analysis to detect memory access errors
Memory corruption errors lead to non-deterministic, elusive crashes. This paper describes ARCHER (ARray CHeckER) a static, effective memory access checker. ARCHER uses path-sensit...
Yichen Xie, Andy Chou, Dawson R. Engler