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107
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DAC
2007
ACM
16 years 3 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
ICES
2000
Springer
140views Hardware» more  ICES 2000»
15 years 5 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ASPDAC
1998
ACM
65views Hardware» more  ASPDAC 1998»
15 years 6 months ago
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
Miyako Tandai, Takao Shinsha
BMCBI
2007
151views more  BMCBI 2007»
15 years 2 months ago
Identification of hot regions in protein-protein interactions by sequential pattern mining
Background: Identification of protein interacting sites is an important task in computational molecular biology. As more and more protein sequences are deposited without available...
Chen-Ming Hsu, Chien-Yu Chen, Baw-Jhiune Liu, Chih...
121
Voted
SAC
2004
ACM
15 years 7 months ago
Guiding motif discovery by iterative pattern refinement
In this paper, we demonstrate that the performance of a motif discovery algorithm can be significantly improved by embedding it into a novel framework that effectively guides the ...
Zhiping Wang, Mehmet M. Dalkilic, Sun Kim