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ICCD
2007
IEEE
161views Hardware» more  ICCD 2007»
16 years 1 months ago
Scan chain design for three-dimensional integrated circuits (3D ICs)
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
ICCAD
2008
IEEE
122views Hardware» more  ICCAD 2008»
16 years 1 months ago
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
Qiang Ma, Evangeline F. Y. Young
ICCAD
2006
IEEE
139views Hardware» more  ICCAD 2006»
16 years 1 months ago
Analog placement with symmetry and other placement constraints
In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for ...
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N...
RECOMB
2010
Springer
15 years 11 months ago
Incremental Signaling Pathway Modeling by Data Integration
Constructing quantitative dynamic models of signaling pathways is an important task for computational systems biology. Pathway model construction is often an inherently incremental...
Geoffrey Koh, David Hsu, P. S. Thiagarajan
AOSD
2009
ACM
15 years 11 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
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