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ICESS
2007
Springer
15 years 5 months ago
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing thei...
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zaman...
TOG
2012
242views Communications» more  TOG 2012»
13 years 1 months ago
Precomputed acceleration noise for improved rigid-body sound
We introduce an efficient method for synthesizing acceleration noise – sound produced when an object experiences abrupt rigidbody acceleration due to collisions or other contac...
Jeffrey N. Chadwick, Changxi Zheng, Doug L. James
ASAP
2008
IEEE
186views Hardware» more  ASAP 2008»
15 years 5 months ago
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-thro...
Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberla...
GLOBECOM
2007
IEEE
15 years 3 months ago
Accelerating Service Discovery in Ad-Hoc Zero Configuration Networking
Zero Configuration Networking (Zeroconf) assigns IP addresses and host names, and discovers service without a central server. Zeroconf can be used in wireless mobile ad-hoc network...
Se Gi Hong, Suman Srinivasan, Henning Schulzrinne
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
15 years 3 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich