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» The Accelerated Euclidean Algorithm
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ISW
2001
Springer
15 years 3 months ago
Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator B
In this paper, we present the results of the first phase of a project aimed at implementing a full suite of IPSec cryptographic transformations in reconfigurable hardware. Full imp...
Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Sc...
SIGGRAPH
1996
ACM
15 years 3 months ago
Hierarchical Image Caching for Accelerated Walkthroughs of Complex Environments
We present a new method that utilizes path coherence to accelerate walkthroughs of geometrically complex static scenes. As a preprocessing step, our method constructs a BSP-tree t...
Jonathan Shade, Dani Lischinski, David Salesin, To...
DASFAA
2004
IEEE
169views Database» more  DASFAA 2004»
15 years 3 months ago
Statistic Driven Acceleration of Object-Relational Space-Partitioning Index Structures
Relational index structures, as for instance the Relational Interval Tree or the Linear Quadtree, support efficient processing of queries on top of existing object-relational datab...
Hans-Peter Kriegel, Peter Kunath, Martin Pfeifle, ...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 3 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
CDC
2009
IEEE
114views Control Systems» more  CDC 2009»
15 years 2 months ago
Parametric model order reduction accelerated by subspace recycling
Abstract-- Many model order reduction methods for parameterized systems need to construct a projection matrix V which requires computing several moment matrices of the parameterize...
Lihong Feng, Peter Benner, Jan G. Korvink