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95
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ICIP
2005
IEEE
16 years 2 months ago
Joint source-network error control coding for scalable overlay video streaming
In this paper, we propose a Joint Source-Network error control coding (JSNC) scheme which efficiently integrates scalable video coding, error control coding and overlay infrastruc...
Yufeng Shan, Shivkumar Kalyanaraman, John W. Woods...
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
16 years 1 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...
IEEEPACT
2009
IEEE
15 years 7 months ago
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
Carlos Madriles, Pedro López, Josep M. Codi...
91
Voted
MOBICOM
2006
ACM
15 years 6 months ago
Component based channel assignment in single radio, multi-channel ad hoc networks
In this paper, we consider the channel assignment problem in single radio multi-channel mobile ad-hoc networks. Specifically, we investigate the granularity of channel assignment...
Ramanuja Vedantham, Sandeep Kakumanu, Sriram Laksh...
WMPI
2004
ACM
15 years 6 months ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...