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ASPLOS
1994
ACM
15 years 3 months ago
Compiler Optimizations for Improving Data Locality
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
Steve Carr, Kathryn S. McKinley, Chau-Wen Tseng
HPDC
2007
IEEE
15 years 6 months ago
A fast topology inference: a building block for network-aware parallel processing
Adapting to the network is the key to achieving high performance for communication-intensive applications, including scientific computing, data intensive computing, and multicast...
Tatsuya Shirai, Hideo Saito, Kenjiro Taura
GECCO
2003
Springer
116views Optimization» more  GECCO 2003»
15 years 5 months ago
A Hybrid Genetic Algorithm Based on Complete Graph Representation for the Sequential Ordering Problem
Abstract. A hybrid genetic algorithm is proposed for the sequential ordering problem. It is known that the performance of a genetic algorithm depends on the survival environment an...
Dong-il Seo, Byung Ro Moon
SPAA
2010
ACM
15 years 4 months ago
Towards optimizing energy costs of algorithms for shared memory architectures
Energy consumption by computer systems has emerged as an important concern. However, the energy consumed in executing an algorithm cannot be inferred from its performance alone: i...
Vijay Anand Korthikanti, Gul Agha
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
13 years 11 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang