17409 search results - page 57 / 3482 » The Design and Performance of MedJava |
ISVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-b...
GECCO
2007
Springer
15 years 3 months ago
2007
Springer
This research screens the tuning parameters of a combinatorial optimization heuristic. Specifically, it presents a Design of Experiments (DOE) approach that uses a Fractional Fac...
189
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CASES
2011
ACM
13 years 9 months ago
2011
ACM
This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarc...
HPCA
2000
IEEE
15 years 2 months ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
114
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DAC
2012
ACM
13 years 4 days ago
2012
ACM
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...