867 search results - page 58 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
100
click to vote
HPCA
2000
IEEE
15 years 4 months ago
2000
IEEE
This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
ICPP
1997
IEEE
15 years 4 months ago
1997
IEEE
Most of recent research on distributed shared memory (DSM)systems have focused on either careful design of node controllersor cache coherenceprotocols. Whileevaluating these desig...
DAC
2004
ACM
16 years 24 days ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
ICS
2009
Tsinghua U.
15 years 6 months ago
2009
Tsinghua U.
The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory loc...
140
click to vote
WMPI
2004
ACM
15 years 5 months ago
2004
ACM
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...