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» The Design and Performance of a Conflict-Avoiding Cache
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TC
2011
14 years 6 months ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
CCGRID
2004
IEEE
15 years 3 months ago
Unifier: unifying cache management and communication buffer management for PVFS over InfiniBand
The advent of networking technologies and high performance transport protocols facilitates the service of storage over networks. However, they pose challenges in integration and i...
Jiesheng Wu, Pete Wyckoff, Dhabaleswar K. Panda, R...
ISCA
1995
IEEE
109views Hardware» more  ISCA 1995»
15 years 3 months ago
Next Cache Line and Set Prediction
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald
USENIX
1990
15 years 1 months ago
Efficient User-Level File Cache Management on the Sun Vnode Interface
In developing a distributed file system, there are several good reasons for implementing the client file cache manager as a user-level process. These include ease of implementatio...
David C. Steere, James J. Kistler, Mahadev Satyana...
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
13 years 2 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...