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ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
15 years 9 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
HPDC
1997
IEEE
15 years 9 months ago
Supporting Parallel Applications on Clusters of Workstations: The Intelligent Network Interface Approach
This paper presents a novel networking architecture designed for communication intensive parallel applications running on clusters of workstations (COWs) connected by highspeed ne...
Marcel-Catalin Rosu, Karsten Schwan, Richard Fujim...
IPPS
2007
IEEE
15 years 11 months ago
Experimental Evaluation of Emerging Multi-core Architectures
The trend of increasing speed and complexity in the single-core processor as stated in the Moore’s law is facing practical challenges. As a result, the multi-core processor arch...
Abdullah Kayi, Yiyi Yao, Tarek A. El-Ghazawi, Greg...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 10 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
JPDC
2000
141views more  JPDC 2000»
15 years 4 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...