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JSAT
2008
85views more  JSAT 2008»
15 years 4 months ago
Parallel SAT Solving using Bit-level Operations
We show how to exploit the 32/64 bit architecture of modern computers to accelerate some of the algorithms used in satisfiability solving by modifying assignments to variables in ...
Marijn Heule, Hans van Maaren
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 10 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
VLSID
1997
IEEE
106views VLSI» more  VLSID 1997»
15 years 9 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
S. Ramanathan, V. Visvanathan
IEEEPACT
2009
IEEE
15 years 11 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi
APCSAC
2000
IEEE
15 years 8 months ago
Dataflow Java: Implicitly Parallel Java
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...
Gareth Lee, John Morris