2155 search results - page 134 / 431 » The EM-X Parallel Computer: Architecture and Basic Performan... |
162
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PADS
2006
ACM
15 years 11 months ago
2006
ACM
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
162
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ISCA
2012
IEEE
13 years 7 months ago
2012
IEEE
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
128
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HPCA
2001
IEEE
16 years 5 months ago
2001
IEEE
A new memory subsystem called Memory Expansion Technology (MXT) has been built for compressing main memory contents. MXT effectively doubles the physically available memory. This ...
149
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ET
2007
15 years 4 months ago
2007
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
124
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ICDCSW
2005
IEEE
15 years 10 months ago
2005
IEEE
We have built a router testbed that is connected to the Deter/Emist experimental infrastructure. Our goal is to create a semi-realistic testbed to conduct BGP experiments, measure...