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NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
15 years 9 months ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin
TNN
2008
152views more  TNN 2008»
15 years 4 months ago
Distributed Parallel Support Vector Machines in Strongly Connected Networks
We propose a distributed parallel support vector machine (DPSVM) training mechanism in a configurable network environment for distributed data mining. The basic idea is to exchange...
Yumao Lu, Vwani P. Roychowdhury, L. Vandenberghe
ICPR
2004
IEEE
16 years 6 months ago
An FPGA-Based Architecture for Real Time Image Feature Extraction
We propose a novel FPGA-based architecture for the extraction of four texture features using Gray Level Cooccurrence Matrix (GLCM) analysis. These features are angular second mome...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
LREC
2010
138views Education» more  LREC 2010»
15 years 6 months ago
Corpus Aligner (CorAl) Evaluation on English-Croatian Parallel Corpora
An increasing demand for new language resources of recent EU members and accessing countries has in turn initiated the development of different language tools and resources, such ...
Sanja Seljan, Marko Tadic, Zeljko Agic, Jan Snajde...
149
Voted
EUROPAR
2005
Springer
15 years 10 months ago
Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies
Whereas the established interconnection networks (ICTN) achieve low latency by operating in the linear region, i.e. oversizing the fabric, the recent strict cost and power constrai...
Teresa Nachiondo Frinós, Jose Flich, Jos&ea...