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ICS
2000
Tsinghua U.
15 years 8 months ago
Characterizing processor architectures for programmable network interfaces
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Bae...
IPPS
2009
IEEE
15 years 11 months ago
Throughput-fairness tradeoff in Best Effort flow control for on-chip architectures
We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximi...
Fahimeh Jafari, Mohammad Sadegh Talebi, Mohammad H...
154
Voted
IPPS
2002
IEEE
15 years 10 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 9 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
156
Voted
CLUSTER
2001
IEEE
15 years 8 months ago
SOVIA: A User-level Sockets Layer Over Virtual Interface Architecture
The Virtual Interface Architecture (VIA) is an industry standard user-level communication architecture for system area networks. The VIA provides a protected, directlyaccessible i...
Jin-Soo Kim, Kangho Kim, Sung-In Jung