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IPPS
2002
IEEE
15 years 10 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
IPPS
2000
IEEE
15 years 9 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
IPPS
2010
IEEE
15 years 2 months ago
Characterizing heterogeneous computing environments using singular value decomposition
We consider a heterogeneous computing environment that consists of a collection of machines and task types. The machines vary in capabilities and different task types are better su...
Abdulla Al-Qawasmeh, Anthony A. Maciejewski, Howar...
IPPS
2007
IEEE
15 years 11 months ago
Memory Optimizations For Fast Power-Aware Sparse Computations
— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
Konrad Malkowski, Padma Raghavan, Mary Jane Irwin
131
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IPPS
2003
IEEE
15 years 10 months ago
Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
João M. P. Cardoso