Sciweavers

2155 search results - page 328 / 431
» The EM-X Parallel Computer: Architecture and Basic Performan...
Sort
View
152
Voted
ICS
2005
Tsinghua U.
15 years 10 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
IPPS
2000
IEEE
15 years 9 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
DCOSS
2008
Springer
15 years 6 months ago
Distributed Activity Recognition with Fuzzy-Enabled Wireless Sensor Networks
Wireless sensor nodes can act as distributed detectors for recognizing activities online, with the final goal of assisting the users in their working environment. We propose an act...
Mihai Marin-Perianu, Clemens Lombriser, Oliver Amf...
HPCC
2010
Springer
15 years 3 months ago
Implementation and Evaluation of a NAT-Gateway for the General Internet Signaling Transport Protocol
The IETF's Next Steps in Signaling (NSIS) framework provides an up-to-date signaling protocol suite that can be used to dynamically install, maintain, and manipulate state in ...
Roland Bless, Martin Röhricht
IPPS
2007
IEEE
15 years 11 months ago
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-e...
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas A...