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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
15 years 2 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
MTV
2005
IEEE
81views Hardware» more  MTV 2005»
15 years 3 months ago
Search-Space Optimizations for High-Level ATPG
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architec...
Jorge Campos, Hussain Al-Asaad
DAC
1995
ACM
15 years 1 months ago
Code Optimization Techniques for Embedded DSP Microprocessors
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...
IPPS
2007
IEEE
15 years 4 months ago
Experience of Optimizing FFT on Intel Architectures
Automatic library generators, such as ATLAS [11], Spiral [8] and FFTW [2], are promising technologies to generate efficient code for different computer architectures. The library...
Daniel Orozco, Liping Xue, Murat Bolat, Xiaoming L...
FORMATS
2003
Springer
15 years 3 months ago
Time-Optimal Test Cases for Real-Time Systems
Testing is the primary software validation technique used by industry today, but remains ad hoc, error prone, and very expensive. A promising improvement is to automatically genera...
Anders Hessel, Kim Guldstrand Larsen, Brian Nielse...