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ICMCS
2007
IEEE
144views Multimedia» more  ICMCS 2007»
15 years 3 months ago
A Framework for Modular Signal Processing Systems with High-Performance Requirements
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
Lukas Diduch, Ronald Müller, Gerhard Rigoll
AINA
2009
IEEE
15 years 2 months ago
An Analytical Performance Evaluation for WSNs Using Loop-Free Bellman Ford Protocol
—Although several analytical models have been proposed for wireless sensor networks (WSNs) with different capabilities, very few of them consider the effect of general service di...
Mohammad Baharloo, Reza Hajisheykhi, Mohammad Arjo...
73
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FPGA
2005
ACM
97views FPGA» more  FPGA 2005»
15 years 3 months ago
Techniques for synthesizing binaries to an advanced register/memory structure
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
INFOCOM
1998
IEEE
15 years 1 months ago
Design Considerations for Supporting TCP with Per-Flow Queueing
In this paper, we investigate the extent to which fair queueing (and its variants), in conjunction with appropriately tailored buffer management schemes, can be used to achieve th...
Bernhard Suter, T. V. Lakshman, Dimitrios Stiliadi...
WWIC
2007
Springer
132views Communications» more  WWIC 2007»
15 years 3 months ago
A Quality Adaptation Scheme for Internet Video Streams
We propose a layered quality adaptation scheme for video streams to smooth the short-term oscillations induced by Additive Increase Multiplicative Decrease (AIMD) mechanisms, and e...
Panagiotis Papadimitriou, Vassilis Tsaoussidis