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» The Entropy of FPGA Reconfiguration
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FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
15 years 5 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele
IPPS
2007
IEEE
15 years 7 months ago
A Reconfigurable Load Balancing Architecture for Molecular Dynamics
This paper proposes a novel architecture supporting dynamic load balancing on an FPGA for a Molecular Dynamics algorithm. Load balancing is primarily achieved through the use of s...
Jonathan Phillips, Matthew Areno, Chris Rogers, Ar...
IPPS
2006
IEEE
15 years 7 months ago
Investigation into programmability for layer 2 protocol frame delineation architectures
This paper presents the design and study of reconfigurable architectures for two data-link layer frame delineation techniques used for ATM and GFP. The architectures are targeted ...
Ciaran Toal, Sakir Sezer
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 7 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
DFT
2009
IEEE
178views VLSI» more  DFT 2009»
15 years 8 months ago
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
Bradley F. Dutton, Charles E. Stroud