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NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
13 years 10 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
CN
2000
96views more  CN 2000»
13 years 6 months ago
Dynamic routing and resource allocation in WDM transport networks
This contribution concentrates on dynamic routing in WDM (Wavelength Division Multiplexing) networks. It is shown that a strategy based on precalculated alternatives and an adapti...
Jan Späth
DATE
2009
IEEE
154views Hardware» more  DATE 2009»
14 years 1 months ago
Reliability aware through silicon via planning for 3D stacked ICs
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kua...
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
13 years 11 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
SLIP
2009
ACM
14 years 24 days ago
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim